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gain_min
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3.1
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dict
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06650
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
valid
84.3
35
0.00187
30
90
3.75
182.3652
1,907.538141
-225.52
3.86
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06650", "split": "train", "index": 0, "goal_level": "hard_gain", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target":...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06651
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_power
valid
53.7
4.8
0.0354
30
90
50.42
146.4276
0.030933
-103.58
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06651", "split": "train", "index": 1, "goal_level": "hard_power", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target"...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06652
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_bandwidth
valid
14.2
26.3
8.53
30
90
54.87
60.25104
0.006198
-149.08
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06652", "split": "train", "index": 2, "goal_level": "hard_bandwidth", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "tar...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06653
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_bandwidth
valid
16.3
34.7
13.4
30
90
72.23
48.50496
0.002737
-147.37
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06653", "split": "train", "index": 3, "goal_level": "hard_bandwidth", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "tar...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06654
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
invalid
77.1
20.2
0.00236
30
90
-76.84
36.05508
null
null
66.48
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06654", "split": "train", "index": 4, "goal_level": "hard_gain", "initial_state_class": "invalid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06655
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
invalid
78.1
17.5
0.00325
30
90
-135.06
264.2556
null
null
29.45
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06655", "split": "train", "index": 5, "goal_level": "hard_gain", "initial_state_class": "invalid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06656
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
invalid
79.1
63.1
0.00196
30
90
-29.47
148.2456
null
null
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06656", "split": "train", "index": 6, "goal_level": "hard_gain", "initial_state_class": "invalid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06657
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_power
valid
43.6
4.6
0.0175
30
90
9.5
40.98396
1.521892
84.25
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06657", "split": "train", "index": 7, "goal_level": "hard_power", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target"...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06658
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
invalid
74.5
8.8
0.0111
30
90
-64.06
105.8076
null
null
49.5
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06658", "split": "train", "index": 8, "goal_level": "hard_gain", "initial_state_class": "invalid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06659
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_power
invalid
48.1
6.5
0.00372
30
90
-17.24
23.24124
null
null
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06659", "split": "train", "index": 9, "goal_level": "hard_power", "initial_state_class": "invalid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "targe...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06660
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_gain
valid
70.6
42.6
0.0338
30
90
5.27
53.67672
0.054908
105.84
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06660", "split": "train", "index": 10, "goal_level": "hard_gain", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target"...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06661
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_power
valid
42.4
4.6
0.026
30
90
35.86
170.7204
0.014814
84.91
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06661", "split": "train", "index": 11, "goal_level": "hard_power", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06662
Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV
complex_fully_differential
false
hard_power
valid
13.7
3.8
1.14
30
90
4.69
40.5678
0.043662
111.95
0
circuit_design
{ "task_id": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV__f3db_hardaxis_train__train__06662", "split": "train", "index": 12, "goal_level": "hard_power", "initial_state_class": "valid", "env_kwargs": { "topology": "Fully_differential_folded_cascode_LG_nmos_l1_biasn_biasp_LV", "target...
End of preview. Expand in Data Studio

SLIC data

Analog circuit optimization tasks for multi-turn LLM agents (65 nm bulk CMOS, open predictive model card, ngspice), and the transistor model cards for the technology-node experiments. The code that uses them is the slic-agent repository; slic data downloads the folders below into the layout it expects.

folder content slic data
standard/ training pool, IID and OOD test sets (and the IID subset evaluated during training) used by the paper's main runs --family standard
hard/ harder tasks on the same topologies: one specification starts far from its target (not used in the paper) --family hard
nodes/ the standard IID subset / OOD test tasks rebuilt for 22, 32, 45, 90 and 130 nm --family nodes
ptm-cards/ predictive technology model cards (Spectre syntax) for those nodes --cards
topologies/ one folder per topology: schematic.svg / .png and netlist.scs (the parameterised circuit every task row of that topology carries) —

topologies.csv lists the 41 topologies (34 in-distribution, 7 held out for the OOD tests): circuit kind, signal mode, device count, number of tunable parameters, and links to its schematic and netlist.

Each task folder has its own README (files, row counts, columns), a stats.json (per file and per topology: row count, valid / invalid starts, and mean / median / min / max of the initial metrics and of the target specifications) and SHA256SUMS; the top-level SHA256SUMS covers every file in the repository.

The dataset viewer above shows the standard, hard and nodes task sets (one subset per family, one split per file); every row is one task, with the circuit, the action space, the goal and the simulated starting point in extra_info.

Version. The paper's results were computed on an earlier version of these task sets that contained errors in some circuits and in the measurement; the sets here are the corrected ones, so numbers on them are not directly comparable to the paper's tables.

Licenses. The task sets (standard/, hard/, nodes/) are released under CC BY 4.0. The model cards in ptm-cards/ are the Predictive Technology Model cards of Arizona State University (https://ptm.asu.edu), converted to Spectre syntax with unchanged parameters, and are redistributed under the terms of their origin (free for research use; see the PTM site). See LICENSE.md.

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